Cache memory design presents significant engineering challenges. For example, as cache sizes have increased, the amount of cache memory allocated for storing tags has increased. Tag storage also increases as the degree of set associativity increases. Tag storage can be reduced by increasing block size, for example, but at the expense of reduced cache efficiency. The die area associated with tag storage is not used for storing information to be accessed by a processor or memory controller, and thus is overhead. This overhead will continue to increase as cache sizes continue to increase. Accordingly, there is a need for new cache memory architectures with reduced overhead.
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